Computer Architecture

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Yes. The Computer Architecture quiz is completely free with no signup. Answer the questions, get instant scoring, and earn XP as you go.

Q: What level is the Computer Architecture quiz?

This is a Hard-level quiz. Each question includes the correct answer so you learn as you test yourself, whatever your starting point.

Q: How can I prepare for this quiz?

Review the linked courses and notes for the topic first, then take the quiz to check your understanding. You can retake it anytime to track improvement.

Question 1

What are the three stages of the basic CPU fetch-decode-execute cycle?

Accepted Answer

The instruction cycle: (1) Fetch — the CPU reads the next instruction from memory using the program counter; (2) Decode — the control unit interprets the opcode; (3) Execute — the ALU or other unit performs the operation.

Question 2

What is the fundamental difference between RAM and ROM?

Accepted Answer

RAM (Random Access Memory) is fast, read-write, and volatile — used for currently running programs. ROM (Read-Only Memory) retains data without power and stores firmware like the BIOS/UEFI boot sequence.

Question 3

What is the purpose of cache memory levels L1, L2, and L3?

Accepted Answer

Cache hierarchy exploits locality of reference. L1 (~32KB, ~1ns) is closest to the CPU core. L2 (~256KB, ~3ns) is a backup for L1. L3 (several MB, ~10ns) is shared across cores. RAM access takes ~100ns by comparison.

Question 4

What is the Von Neumann bottleneck?

Accepted Answer

The Von Neumann bottleneck arises because the CPU and memory share a single communication channel. Even with a fast CPU, it stalls waiting for data/instructions from memory. Caches and prefetching mitigate but don't eliminate this.

Question 5

What is the main design philosophy difference between RISC and CISC architectures?

Accepted Answer

RISC (ARM, RISC-V): fewer, simpler instructions → easier pipelining, lower power, used in mobile. CISC (x86): rich instruction set → fewer instructions per program but complex hardware decode. Modern x86 CPUs translate CISC to RISC-like micro-ops internally.

Question 6

What are pipeline hazards in CPU pipelining?

Accepted Answer

Data hazards: next instruction needs a result not yet written. Control hazards: branches disrupt the instruction flow. Structural hazards: two instructions need the same hardware resource simultaneously. Solutions include stalling, forwarding, and branch prediction.

Question 7

What is the decimal value of the binary number 1010?

Accepted Answer

Binary 1010 = 1×2³ + 0×2² + 1×2¹ + 0×2⁰ = 8 + 0 + 2 + 0 = 10 in decimal.

Question 8

What is the output of an AND gate when inputs are A=1 and B=0?

Accepted Answer

An AND gate outputs 1 only when ALL inputs are 1. Truth table: 0 AND 0 = 0, 0 AND 1 = 0, 1 AND 0 = 0, 1 AND 1 = 1. Since B=0, the output is 0.

Question 9

What does Moore's Law observe about transistor density?

Accepted Answer

Gordon Moore (1965) observed transistor counts doubling roughly every two years. This drove decades of performance gains. Physical limits (heat, quantum effects, atomic scale) mean Moore's Law is slowing, driving innovation in 3D stacking and new materials.

Question 10

What is the purpose of virtual memory in operating systems?

Accepted Answer

Virtual memory abstracts physical memory. The OS maps virtual addresses to physical RAM pages (page table). Pages not in RAM are swapped to disk. This enables multiprogramming, memory protection, and simplified program loading.

Computer Architecture

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