Capstone Project: Real CPU Architecture Analysis & Application

Why This Project Exists

You've studied pipeline stages, hazards, cache mapping, virtual memory, I/O systems, parallel processing, and modern CPU architectures. But reading about concepts and applying them to real hardware specifications are two different cognitive experiences.

This capstone project bridges that gap. You will analyze two of the most significant real world processors in current use, design your own comparative framework, apply pipeline and cache concepts to concrete problems, and verify that every number you write traces back to a concept from this course.

Engineers who can read a datasheet and immediately identify which architectural choices produced which specification that's the skill this project develops.

Part 1: Intel Core i7-13700K Deep Analysis

The Intel Core i7-13700K (Raptor Lake, Q4 2022) is a mainstream desktop processor that embodies Intel's hybrid architecture design.

Verified Specifications

Connecting Specifications to Course Concepts

Pipeline (Lesson: CPU Pipeline Stages): The i7-13700K uses a 14–19 stage pipeline in P cores (Golden Cove / Raptor Cove microarchitecture). This depth enables the 5.4 GHz boost clock shorter stages mean faster clocks. The E cores (Gracemont) use a shorter pipeline (~12 stages) prioritizing power efficiency over peak clock.

Hazards (Lesson: Pipeline Hazards & Solutions): Intel's Raptor Cove uses a Tournament branch predictor (TAGE SC L family) achieving 95–99% accuracy on typical workloads. The out of order execution window holds 512 reorder buffer (ROB) entries meaning 512 instructions can be "in flight" simultaneously while the scheduler finds independent work to hide latency.

Cache (Lesson: Cache Memory & Mapping):

• L1 I cache: 48KB, 8-way set associative, 12-cycle fill latency
• L1 D cache: 48KB, 12-way set associative, 5-cycle hit latency
• L2: 2MB, 16-way set associative, ~14-cycle hit latency
• L3: 30MB, 24-way set associative, ~40-cycle hit latency
• All use PLRU (Pseudo LRU) replacement policy
• MESI protocol for cache coherence across all 16 physical cores

Virtual Memory (Lesson: Virtual Memory & Paging): Supports 4-level and 5-level paging (LA57 for 57-bit virtual addresses 128 PB virtual space). Includes a 2,048-entry L2 TLB for 4KB pages.

I/O (Lesson: I/O Systems, Interrupts & DMA): The APIC handles 256 interrupt vectors with hardware priority levels. PCIe 5.0 ×16 provides 64 GB/s DMA bandwidth to the discrete GPU; PCIe 4.0 ×4 to NVMe SSDs provides up to 7 GB/s DMA bandwidth.

Parallel Processing (Lesson: Parallel Processing & Multicore): The hybrid P+E core design directly implements Flynn's MIMD taxonomy. Intel's Thread Director (hardware telemetry) assists the Windows 11/Linux 5.18+ scheduler in assigning tasks to appropriate core types. Hyperthreading on P cores provides 2-way SMT.

Part 2: Apple M3 Pro Analysis & Intel Comparison

The Apple M3 Pro (November 2023, TSMC 3nm N3B) represents the ARM architectural philosophy applied to mainstream laptop computing.

Verified Specifications

Architectural Trade off Comparison

Key trade offs Apple made:

1. Unified Memory vs Discrete GPU VRAM: Apple's UMA means the 18 GB is shared between CPU and GPU. A workstation GPU (RTX 4090) has 24 GB dedicated VRAM + 32+ GB system RAM. For AI inference and video editing, UMA is often faster (no PCIe copy). For high end gaming, dedicated VRAM with >32 GB capacity wins.

2. ARM ISA vs x86-64: Apple's M3 Pro has ~30% better performance per watt than the i7-13700K. But x86-64 native compatibility matters some professional software (older CAD tools, Windows only applications) requires Rosetta 2 translation or virtualization, adding overhead.

3. 150 GB/s vs ~90 GB/s bandwidth: The M3 Pro's LPDDR5 on package memory provides dramatically higher bandwidth than the i7-13700K's off die DDR5-5600 (~89 GB/s). This benefits GPU rendering, video transcoding, and memory bound workloads.

4. Neural Engine: The 16-core Neural Engine handles Core ML inference workloads (image recognition, LLM inference) at 18 TOPS with vastly better power efficiency than running the same work on CPU or GPU. The i7-13700K has no dedicated NPU (Neural Processing Unit) Intel's Meteor Lake added one in 2023.

Part 3: Architecture Comparison Table (Your Framework)

Use this table as a starting point. Extend it with your own research:

Part 4: Pipeline Hazard Application Exercise

Consider these five sequential instructions on a 5-stage RISC pipeline (MIPS like):

I1: ADD  R1, R2, R3   # R1 = R2 + R3
I2: SUB  R4, R1, R5   # R4 = R1 - R5   ← reads R1 (written by I1)
I3: AND  R6, R4, R7   # R6 = R4 & R7   ← reads R4 (written by I2)
I4: LW   R8, 0(R6)    # R8 = Memory[R6]← reads R6 (written by I3)
I5: ADD  R9, R8, R1   # R9 = R8 + R1   ← reads R8 (written by I4), reads R1 (written by I1)

RAW Hazard Analysis

Key finding: Only the I4 → I5 load use hazard requires an unavoidable stall. All other RAW hazards are resolved by forwarding (EX/MEM → EX path). Without forwarding, I1→I2 and I2→I3 would each require 2 stall cycles, and I3→I4 would require 1 stall a total of 5 wasted cycles reduced to 1.

Pipeline execution timeline with forwarding + 1 load use stall:

Bold = forwarding; stall = 1 inserted bubble due to load use hazard

Part 5: Cache Calculation Exercise

Given: A 4-way set associative cache with:

• Total size: 32 KB (32,768 bytes)
• Cache line (block) size: 64 bytes
• Associativity: 4-way
• Address space: 64-bit

Step by Step Calculation

Step 1: Number of cache lines total

Total lines = Cache size / Line size = 32,768 / 64 = 512 lines

Step 2: Number of sets

Sets = Total lines / Associativity = 512 / 4 = 128 sets

Step 3: Offset bits (bits needed to address one byte within a 64-byte line)

Offset bits = log₂(64) = 6 bits

Step 4: Index bits (bits needed to select one of 128 sets)

Index bits = log₂(128) = 7 bits

Step 5: Tag bits (remaining bits identify which memory block)

Tag bits = 64 - 7 - 6 = 51 bits

Summary Table:

Verification: 6 + 7 + 51 = 64 bits ✓

What You Learned: Course Recap

This course covered the complete picture of how modern processors work:

The unifying insight: Every architectural decision in a CPU pipeline depth, cache size, branch predictor complexity, core count, ISA choice is a trade off. Performance vs. power. Throughput vs. latency. Complexity vs. reliability. The engineer's job is to understand which trade offs serve the target use case.

A smartphone processor and a server processor can both be "great CPUs" while making almost entirely opposite architectural choices. The measure of mastery is knowing why those choices differ and this course has given you exactly that foundation.