Instruction Set Architecture: RISC vs. CISC

Two Languages, One Message

In the 1800s, wealthy people sent long, elegant telegrams with complete sentences and nuanced meaning: "I am writing to inform you that I shall be arriving by the morning train on the fourteenth of this month." It was expressive, precise, and rich.

The telegraph operator, paid by the word, translated this to telegram English: "ARRIVING 14TH MORNING TRAIN." Same message. Far fewer words. Completely understood by the recipient.

CISC and RISC are like these two communication styles — but for CPUs. CISC (Complex Instruction Set Computer) gives the processor rich, multi-step instructions, like full sentences. RISC (Reduced Instruction Set Computer) uses short, simple instructions, like telegram words. Both compute the same things. They take fundamentally different philosophical paths to get there.

And the punchline that resolves the debate: your Intel laptop secretly speaks RISC internally — it just accepts CISC instructions at the door.

What an ISA Defines

An Instruction Set Architecture (ISA) is the formal contract between software and hardware. It specifies:

• Instructions: what operations the CPU can execute (ADD, LOAD, BRANCH, CALL)
• Data types: which integer and floating-point formats are natively supported
• Registers: how many, what size, what special purposes
• Addressing modes: how operands (data) are specified in instructions
• Memory model: how load/store operations work, alignment rules
• Exceptions and interrupts: how faults and external events are handled

The ISA is not the chip. It is the specification of the chip's behavior. Intel can (and has) redesigned the internal organization of its x86 processors completely while keeping the ISA identical — ensuring every x86 program from 1978 still runs on a 2025 Core i9.

CISC: Complex Instruction Set Computer

Origin: The mainframe and minicomputer era of the 1960s–1970s. Memory was expensive and slow. Compilers were primitive. Programmers wrote in assembly. The solution was to pack as much work as possible into each instruction, so programs used fewer instructions and occupied less memory.

The philosophy: Give the programmer (or compiler) high-level, powerful instructions that can directly manipulate memory, perform loops, or move blocks of data in a single operation.

CISC Characteristics

• Variable-length instructions: x86 instructions range from 1 to 15 bytes in length
• Memory-to-memory operations: An instruction like ADD [0x1000], [0x2000] adds the value at one memory address to another — directly, without loading into registers first
• Complex addressing modes: MOV EAX, [EBX + ECX*4 + 8] — base register + scaled index + offset, all in one instruction
• Hundreds of instructions: x86 has over 1,000 distinct instructions, including specialized ones like ENTER (creates a stack frame), REP MOVS (block memory copy), and AESIMC (AES key expansion)

CISC Example (x86)

; Multiply a by 5 and store in b (CISC style — one instruction handles memory directly)
IMUL EAX, DWORD PTR [a], 5   ; EAX = memory[a] * 5
MOV  DWORD PTR [b], EAX      ; store result to memory[b]

Real CISC Processors

• Intel x86 / x86-64: Core i3/i5/i7/i9, Xeon (desktops, laptops, servers)
• AMD x86-64: Ryzen, EPYC (desktops, laptops, servers)
• Both companies control ~99% of the x86-64 market

RISC: Reduced Instruction Set Computer

Origin: Research at Stanford (MIPS project, 1981) and UC Berkeley (RISC project, 1980). Led by John Hennessy (Stanford) and David Patterson (Berkeley) — who later won the 2017 Turing Award for this work.

The insight: most programs use only a small subset of available instructions most of the time. Complex instructions that take multiple memory accesses are hard to pipeline and slow the entire chip down.

The philosophy: Use simple, uniform instructions that each complete in exactly one cycle. Let the compiler generate more instructions if needed — but make each instruction blazing fast.

RISC Characteristics

• Fixed-length instructions: ARM64 (AArch64) uses exactly 4 bytes (32 bits) per instruction — always
• Load/Store architecture: Only LOAD and STORE instructions access memory. All arithmetic operates on registers only
• More registers: ARM64 has 31 general-purpose 64-bit registers (X0–X30) vs. x86's 16
• Simple addressing modes: Fewer, simpler ways to specify operands
• Fewer instructions: ARM64 has approximately 200–300 commonly used instructions
• Highly pipelined: Uniform instruction length and simple decode enable deeper, faster pipelines

RISC Example (ARM64)

// Multiply a by 5 and store in b (RISC style — explicit load, compute, store)
LDR  X0, [X1]          // Load 'a' from memory into register X0
MOV  X2, #5            // Load immediate value 5 into register X2
MUL  X0, X0, X2        // X0 = X0 * X2  (register operation only)
STR  X0, [X3]          // Store result from X0 to memory address of 'b'

More instructions, but each one is simple and executes in one cycle. The pipeline runs at full speed.

The RISC vs. CISC Debate — Resolved

The 1980s and 1990s saw fierce academic and industry debate about which philosophy would win. The answer turned out to be: both, at the same time.

Modern x86: CISC on the Outside, RISC on the Inside

Starting with the Intel Pentium Pro (1995), Intel implemented a revolutionary technique: micro-operation (µop) translation. The chip's front-end decoder accepts complex, variable-length CISC instructions and internally translates them into simple, fixed-size RISC-like micro-ops before passing them to the execution engine.

The result: software sees a CISC machine (x86 compatibility maintained). The hardware runs like a RISC machine (simple µops, deep pipeline, out-of-order execution). Best of both worlds.

Apple Silicon: The ARM Triumph

In June 2020, Apple announced it was abandoning Intel processors for its Macs in favor of ARM-based Apple Silicon. The M1 chip shipped in November 2020.

The result stunned the industry:

• Apple M1 (2020): ARM64 (RISC), TSMC 5nm, 16 billion transistors
• Delivered performance comparable to Intel Core i9 at 1/4 the power consumption
• The MacBook Air with M1 had no fan — the chip ran cool enough without active cooling
• The Mac Pro with M2 Ultra (2023) uses 192GB unified memory and delivers workstation performance in a desktop form factor

Why could ARM (RISC) beat Intel (CISC)? Because Apple designed the entire system — CPU, GPU, memory, neural engine — as a unified chip (System on Chip, SoC). The RISC ISA's simplicity and power efficiency were essential enablers.

RISC-V: The Open-Source ISA

While x86 is owned by Intel/AMD and ARM requires a license from Arm Ltd., RISC-V (pronounced "RISC Five") is a completely open, royalty-free ISA developed at UC Berkeley in 2010.

Why it matters:

• Any company can design a RISC-V processor without paying licensing fees
• Google uses RISC-V in the Titan security chip in Pixel phones
• NVIDIA uses RISC-V cores in its GPU firmware
• Western Digital deploys RISC-V in its SSD controllers
• China's semiconductor industry is heavily investing in RISC-V to reduce dependency on Western IP

RISC-V uses a modular base ISA with optional extensions (M = multiply/divide, A = atomic, F = single-precision float, D = double-precision float, V = vector).

Addressing Modes

Both CISC and RISC need to specify where operands come from. These are the addressing modes:

x86's scaled indexed mode is extremely powerful — and a perfect example of CISC complexity. Implementing it requires significant decoder hardware that ARM simply doesn't need.

RISC vs. CISC Comparison Table

Key Takeaways

• An ISA defines the programmer-visible contract: instructions, registers, data types, addressing modes, and exception behavior
• CISC (x86, x86-64) uses variable-length, powerful instructions that can operate directly on memory — designed for code density in the memory-scarce 1970s
• RISC (ARM, MIPS, RISC-V) uses fixed-length, simple instructions operating only on registers — designed for pipeline efficiency and compiler-friendly code generation
• The debate is resolved: modern x86 CPUs translate CISC instructions into internal RISC-like µops — CISC interface, RISC execution engine
• Apple Silicon (ARM64 RISC) delivers comparable performance to Intel (x86-64 CISC) at 1/4 the power — proving RISC's efficiency advantage is real
• RISC-V is the open-source ISA gaining rapid momentum — used by Google, NVIDIA, Western Digital, and China's semiconductor industry
• Addressing modes are how instructions specify operands: CISC supports many complex modes; RISC uses simple register + offset