Sequential Circuits and Flip-Flops

The Circuit That Forgets Everything

Build a combinational circuit — a full adder, a multiplexer, a decoder — and it has a peculiar property: it has no memory whatsoever. Remove the inputs, and the outputs go dark. Change the inputs, and the outputs instantly change to reflect only the new values. The circuit doesn't remember what happened a millisecond ago. It doesn't even know time exists.

This is useful for arithmetic. But a computer needs to remember things. It needs to hold the result of the last calculation while it fetches the next instruction. It needs to track whether a loop has finished. It needs to store a variable across thousands of clock cycles.

The solution is a sequential circuit — a circuit whose output depends on both the current inputs AND the history of past inputs. It has state. It remembers.

The key insight: you can build memory from logic gates by feeding the output of a circuit back into its own input. When you do this carefully, the circuit can latch onto a value and hold it indefinitely, even when the original inputs change.

Why Sequential Logic Exists: The Memory Problem

Consider a CPU executing the instruction x = x + 1. It must:

1. Read the current value of x from a register
2. Pass it through the ALU (add 1)
3. Write the result back to the same register

Steps 1 and 3 require the same memory location to hold a value across time. Combinational logic cannot do this — it computes and immediately forgets. Flip-flops solve this problem.

"A flip-flop is a 1-bit memory cell. A CPU register is 64 flip-flops. A CPU with 16 general-purpose registers has 1,024 flip-flops just for register storage."

SR Latch: The Simplest Memory Element

The SR latch (Set-Reset latch) is the foundation of all sequential circuits. It is built from two cross-coupled NOR gates.

S ──→ [NOR] ──→ Q
       ↑  ↓
R ──→ [NOR] ──→ Q̄

• S=1, R=0: Q is forced to 1 (Set)
• S=0, R=1: Q is forced to 0 (Reset)
• S=0, R=0: Q holds its previous value (memory!)
• S=1, R=1: Forbidden state (both outputs forced to 0, undefined behavior when inputs return to 00)

The cross-coupling is the magic: each gate's output feeds back as the other gate's input, creating a stable feedback loop that holds state.

D Flip-Flop: The Universal Memory Cell

The SR latch is asynchronous — it changes state whenever S or R change. Synchronous circuits need an element that only updates at a specific time: the clock edge.

The D flip-flop (Data flip-flop) captures the value of its D input on the rising edge of the clock and holds it until the next rising edge.

• D = Data input (the bit to be stored)
• CLK = Clock signal
• Q = Stored output
• Q̄ = Inverted output

Behavior: On each ↑ clock edge, Q ← D. Between clock edges, Q is frozen.

Implementation: A D flip-flop is essentially two SR latches in a master-slave configuration controlled by the clock. When CLK=0, the master latch is transparent; when CLK=1, the slave latch captures the master's output.

Flip-Flop Timing Diagram

At each rising clock edge, Q captures the current value of D and holds it.

JK Flip-Flop

The JK flip-flop eliminates the forbidden state of the SR latch. J (Set) and K (Reset) correspond to S and R, but when both J=1 and K=1, the output toggles (Q becomes Q̄).

JK flip-flops were widely used before D flip-flops became standard. Today they appear primarily in counters and certain FSM (Finite State Machine) designs.

T Flip-Flop

The T (Toggle) flip-flop has a single input T:

• T=0: Q holds
• T=1: Q toggles on each clock edge

It is a JK flip-flop with J=K=T. Primary use: binary counters — connect T=1 permanently and Q toggles every clock cycle, dividing the clock frequency by 2.

Registers: N Flip-Flops, N Bits

A register is simply N D flip-flops sharing a common clock, storing an N-bit value.

An 8-bit register stores one byte. A 64-bit register stores a 64-bit integer (like long in Java or int64_t in C).

Modern CPUs have:

• x86-64: 16 general-purpose 64-bit registers (RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP, R8–R15) = 1,024 flip-flops just for GP registers
• ARM Cortex-A: 31 general-purpose 64-bit registers = 1,984 flip-flops
• Plus floating-point, vector (SIMD), and status registers — total register flip-flop count is in the thousands

Shift Register

A shift register is a chain of D flip-flops where each flip-flop's Q output is connected to the next flip-flop's D input. On each clock edge, data shifts one position left (or right).

Uses:

• Serial-to-parallel conversion (receiving data one bit at a time over UART/SPI/I2C)
• Data delay lines
• CRC (Cyclic Redundancy Check) computation for error detection

Binary Counter

A 4-bit counter uses 4 T flip-flops and counts from 0000 to 1111 (0 to 15), then wraps back to 0000.

FF0: T=1 always → toggles every clock → LSB (1, 0, 1, 0...)
FF1: T=Q0 → toggles when FF0 output goes LOW
FF2: T=Q1 → toggles when FF1 output goes LOW
FF3: T=Q2 → toggles when FF2 output goes LOW

Output sequence: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1...

CPU use: Program counter increments by 1 (or 2, 4) each cycle; loop counters in hardware multiply units; timer circuits.

Clock Signal and Synchronization

The clock is a square wave that synchronizes all sequential elements in a chip. Every D flip-flop in the CPU updates simultaneously on the rising (or falling) edge.

A modern CPU's clock distribution network:

• Intel Core i9-13900K: up to 5.8 GHz (5,800,000,000 rising edges per second)
• The clock signal is distributed from a Phase-Locked Loop (PLL) to every flip-flop on the die
• Clock skew — the tiny differences in arrival time across the chip — must be kept below the clock period

Setup Time and Hold Time

For a D flip-flop to reliably capture data:

• Setup time (tsu): D must be stable for at least this long before the clock edge (~20–100 ps)
• Hold time (th): D must remain stable for at least this long after the clock edge (~10–50 ps)

Violate these constraints and the flip-flop enters a metastable state — an undefined output that resolves randomly. Metastability is a real engineering concern in asynchronous clock domain crossing.

Flip-Flop Comparison Table

Key Takeaways

• Sequential circuits have state — their outputs depend on both current inputs AND past history
• SR latch is the simplest memory element, built from two cross-coupled NOR gates — the foundation of all flip-flops
• D flip-flop captures its input on the clock edge and holds it — the universal building block for CPU registers
• JK flip-flop extends SR with a toggle mode; T flip-flop toggles on each clock pulse (used in counters)
• A CPU register is N D flip-flops sharing a clock; an Intel Core i9 has 1,024+ flip-flops in general-purpose registers alone
• Setup time and hold time are critical timing constraints — violating them causes metastability
• The clock signal synchronizes all sequential logic; a 5.8 GHz CPU has 5.8 billion synchronization events per second
• All of RAM, CPU registers, and cache are ultimately made from circuits derived from the humble SR latch